Novel Defect Terminolgy Beside Evaluation And Design Fault Tolerant Logic Gates In Quantum-Dot Cellular Automata

Quantum dot Cellular Automata (QCA) is one of the important nano-level technologies for implementation of both combinational and sequential systems. QCA have the potential to achieve low power dissipation and operate high speed at THZ frequencies. However large probability of occurrence fabrication defects in QCA, is a fundamental challenge to use this emerging technology. Because of these various defects, it is necessary to obtain exhaustive recognition about these defects. In this paper a complete survey of different QCA faults are presented first. Then some techniques to improve fault tolerance in QCA circuits explained. The effects of missing cell as an important fault on XOR gate that is one of important basic building block in QCA technology is then discussed by exhaustive simulations. Improvement technique is then applied to these XOR structures and then structures are resimulated to measure their fault tolerance improvement due to using these fault tolerance technique. The result show that different QCA XOR gates have different sensitivity against this fault. After using improvement technique, the tolerance of XOR gates have been increased, furthermore in terms of sensitivity against this defect XORs show similar behavior that indicate the effectiveness of improvement have been made

A hybrid RISC-V architecture supporting mixed timing-critical and high performance workloads

The hardware platforms available today for embedded systems are already capable of implementing different classes of applications. These can be real-time applications, in which compliance with given time limits must be guaranteed, and high-performance applications, in which the aim is to execute as many instructions as possible per unit of time. The goal of this work is to propose a hybrid hardware platform that is capable of executing the above two classes of applications without suffering from mutually negative timing predictability and execution time optimization requirements. This work presents a set of requirements for such a hybrid hardware platform for embedded systems. Based on these requirements, various existing platforms, ranging from high-performance embedded to fully time-predictable architectures, are analyzed and compared. Based on this analysis, a new hybrid architecture is proposed that can switch between a real-time and high-performance execution mode at runtime

A RISC-V based platform supporting mixed timing-critical and high performance workloads

Existing hardware platforms are typically optimized for either real-time or high-performance applications, which poses challenges when running a mix of both on the same platform. This work aims to address this issue by proposing a hybrid platform that can effectively execute both types of applications without compromising timing predictability or performance optimization. The proposed solution presents a hybrid HW/SW architecture template capable of dynamically switching between real-time and high-performance execution modes at runtime. The integration and implementation of this architecture template are described on an FPGA, utilizing an open-source RISC-V processor system and FreeRTOS as the software management layer. We have successfully applied the TACLe benchmark suite for the evaluation of our proposed approach. Through an integrated measurement infrastructure, the software functionality, execution timing, and switching times are analyzed on a single-core implementation of the proposed architecture templat